-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"

-- DATE "12/11/2021 23:05:25"

-- 
-- Device: Altera EP4CE10E22C8 Package TQFP144
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY CYCLONEIVE;
LIBRARY IEEE;
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	decode IS
    PORT (
	cntin1 : IN std_logic_vector(3 DOWNTO 0);
	cntin2 : IN std_logic_vector(3 DOWNTO 0);
	ledout1 : BUFFER std_logic_vector(6 DOWNTO 0);
	ledout2 : BUFFER std_logic_vector(6 DOWNTO 0)
	);
END decode;

-- Design Ports Information
-- ledout1[0]	=>  Location: PIN_43,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledout1[1]	=>  Location: PIN_34,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledout1[2]	=>  Location: PIN_135,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledout1[3]	=>  Location: PIN_44,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledout1[4]	=>  Location: PIN_38,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledout1[5]	=>  Location: PIN_46,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledout1[6]	=>  Location: PIN_80,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledout2[0]	=>  Location: PIN_52,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledout2[1]	=>  Location: PIN_100,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledout2[2]	=>  Location: PIN_58,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledout2[3]	=>  Location: PIN_60,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledout2[4]	=>  Location: PIN_126,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledout2[5]	=>  Location: PIN_10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- ledout2[6]	=>  Location: PIN_120,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- cntin1[0]	=>  Location: PIN_90,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- cntin1[1]	=>  Location: PIN_91,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- cntin1[2]	=>  Location: PIN_39,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- cntin1[3]	=>  Location: PIN_66,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- cntin2[0]	=>  Location: PIN_104,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- cntin2[1]	=>  Location: PIN_106,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- cntin2[2]	=>  Location: PIN_103,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- cntin2[3]	=>  Location: PIN_99,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF decode IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_cntin1 : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_cntin2 : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_ledout1 : std_logic_vector(6 DOWNTO 0);
SIGNAL ww_ledout2 : std_logic_vector(6 DOWNTO 0);
SIGNAL \ledout1[0]~output_o\ : std_logic;
SIGNAL \ledout1[1]~output_o\ : std_logic;
SIGNAL \ledout1[2]~output_o\ : std_logic;
SIGNAL \ledout1[3]~output_o\ : std_logic;
SIGNAL \ledout1[4]~output_o\ : std_logic;
SIGNAL \ledout1[5]~output_o\ : std_logic;
SIGNAL \ledout1[6]~output_o\ : std_logic;
SIGNAL \ledout2[0]~output_o\ : std_logic;
SIGNAL \ledout2[1]~output_o\ : std_logic;
SIGNAL \ledout2[2]~output_o\ : std_logic;
SIGNAL \ledout2[3]~output_o\ : std_logic;
SIGNAL \ledout2[4]~output_o\ : std_logic;
SIGNAL \ledout2[5]~output_o\ : std_logic;
SIGNAL \ledout2[6]~output_o\ : std_logic;
SIGNAL \cntin1[3]~input_o\ : std_logic;
SIGNAL \cntin1[1]~input_o\ : std_logic;
SIGNAL \cntin1[0]~input_o\ : std_logic;
SIGNAL \cntin1[2]~input_o\ : std_logic;
SIGNAL \Mux6~0_combout\ : std_logic;
SIGNAL \Mux5~0_combout\ : std_logic;
SIGNAL \Mux4~0_combout\ : std_logic;
SIGNAL \Mux3~0_combout\ : std_logic;
SIGNAL \Mux2~0_combout\ : std_logic;
SIGNAL \Mux1~0_combout\ : std_logic;
SIGNAL \Mux0~0_combout\ : std_logic;
SIGNAL \cntin2[0]~input_o\ : std_logic;
SIGNAL \cntin2[3]~input_o\ : std_logic;
SIGNAL \cntin2[1]~input_o\ : std_logic;
SIGNAL \cntin2[2]~input_o\ : std_logic;
SIGNAL \Mux13~0_combout\ : std_logic;
SIGNAL \Mux12~0_combout\ : std_logic;
SIGNAL \Mux11~0_combout\ : std_logic;
SIGNAL \Mux10~0_combout\ : std_logic;
SIGNAL \Mux9~0_combout\ : std_logic;
SIGNAL \Mux8~0_combout\ : std_logic;
SIGNAL \Mux7~0_combout\ : std_logic;
SIGNAL \ALT_INV_Mux7~0_combout\ : std_logic;
SIGNAL \ALT_INV_Mux8~0_combout\ : std_logic;
SIGNAL \ALT_INV_Mux9~0_combout\ : std_logic;
SIGNAL \ALT_INV_Mux10~0_combout\ : std_logic;
SIGNAL \ALT_INV_Mux11~0_combout\ : std_logic;
SIGNAL \ALT_INV_Mux12~0_combout\ : std_logic;
SIGNAL \ALT_INV_Mux0~0_combout\ : std_logic;
SIGNAL \ALT_INV_Mux1~0_combout\ : std_logic;
SIGNAL \ALT_INV_Mux2~0_combout\ : std_logic;
SIGNAL \ALT_INV_Mux3~0_combout\ : std_logic;
SIGNAL \ALT_INV_Mux4~0_combout\ : std_logic;
SIGNAL \ALT_INV_Mux5~0_combout\ : std_logic;

BEGIN

ww_cntin1 <= cntin1;
ww_cntin2 <= cntin2;
ledout1 <= ww_ledout1;
ledout2 <= ww_ledout2;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
\ALT_INV_Mux7~0_combout\ <= NOT \Mux7~0_combout\;
\ALT_INV_Mux8~0_combout\ <= NOT \Mux8~0_combout\;
\ALT_INV_Mux9~0_combout\ <= NOT \Mux9~0_combout\;
\ALT_INV_Mux10~0_combout\ <= NOT \Mux10~0_combout\;
\ALT_INV_Mux11~0_combout\ <= NOT \Mux11~0_combout\;
\ALT_INV_Mux12~0_combout\ <= NOT \Mux12~0_combout\;
\ALT_INV_Mux0~0_combout\ <= NOT \Mux0~0_combout\;
\ALT_INV_Mux1~0_combout\ <= NOT \Mux1~0_combout\;
\ALT_INV_Mux2~0_combout\ <= NOT \Mux2~0_combout\;
\ALT_INV_Mux3~0_combout\ <= NOT \Mux3~0_combout\;
\ALT_INV_Mux4~0_combout\ <= NOT \Mux4~0_combout\;
\ALT_INV_Mux5~0_combout\ <= NOT \Mux5~0_combout\;

-- Location: IOOBUF_X5_Y0_N23
\ledout1[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \Mux6~0_combout\,
	devoe => ww_devoe,
	o => \ledout1[0]~output_o\);

-- Location: IOOBUF_X0_Y5_N16
\ledout1[1]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_Mux5~0_combout\,
	devoe => ww_devoe,
	o => \ledout1[1]~output_o\);

-- Location: IOOBUF_X11_Y24_N16
\ledout1[2]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_Mux4~0_combout\,
	devoe => ww_devoe,
	o => \ledout1[2]~output_o\);

-- Location: IOOBUF_X5_Y0_N16
\ledout1[3]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_Mux3~0_combout\,
	devoe => ww_devoe,
	o => \ledout1[3]~output_o\);

-- Location: IOOBUF_X1_Y0_N23
\ledout1[4]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_Mux2~0_combout\,
	devoe => ww_devoe,
	o => \ledout1[4]~output_o\);

-- Location: IOOBUF_X7_Y0_N2
\ledout1[5]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_Mux1~0_combout\,
	devoe => ww_devoe,
	o => \ledout1[5]~output_o\);

-- Location: IOOBUF_X34_Y7_N9
\ledout1[6]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_Mux0~0_combout\,
	devoe => ww_devoe,
	o => \ledout1[6]~output_o\);

-- Location: IOOBUF_X16_Y0_N9
\ledout2[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \Mux13~0_combout\,
	devoe => ww_devoe,
	o => \ledout2[0]~output_o\);

-- Location: IOOBUF_X34_Y17_N2
\ledout2[1]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_Mux12~0_combout\,
	devoe => ww_devoe,
	o => \ledout2[1]~output_o\);

-- Location: IOOBUF_X21_Y0_N9
\ledout2[2]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_Mux11~0_combout\,
	devoe => ww_devoe,
	o => \ledout2[2]~output_o\);

-- Location: IOOBUF_X23_Y0_N9
\ledout2[3]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_Mux10~0_combout\,
	devoe => ww_devoe,
	o => \ledout2[3]~output_o\);

-- Location: IOOBUF_X16_Y24_N2
\ledout2[4]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_Mux9~0_combout\,
	devoe => ww_devoe,
	o => \ledout2[4]~output_o\);

-- Location: IOOBUF_X0_Y18_N16
\ledout2[5]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_Mux8~0_combout\,
	devoe => ww_devoe,
	o => \ledout2[5]~output_o\);

-- Location: IOOBUF_X23_Y24_N9
\ledout2[6]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_Mux7~0_combout\,
	devoe => ww_devoe,
	o => \ledout2[6]~output_o\);

-- Location: IOIBUF_X28_Y0_N1
\cntin1[3]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_cntin1(3),
	o => \cntin1[3]~input_o\);

-- Location: IOIBUF_X34_Y12_N1
\cntin1[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_cntin1(1),
	o => \cntin1[1]~input_o\);

-- Location: IOIBUF_X34_Y12_N8
\cntin1[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_cntin1(0),
	o => \cntin1[0]~input_o\);

-- Location: IOIBUF_X1_Y0_N15
\cntin1[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_cntin1(2),
	o => \cntin1[2]~input_o\);

-- Location: LCCOMB_X3_Y1_N16
\Mux6~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \Mux6~0_combout\ = (\cntin1[3]~input_o\) # ((\cntin1[1]~input_o\ & ((!\cntin1[2]~input_o\) # (!\cntin1[0]~input_o\))) # (!\cntin1[1]~input_o\ & ((\cntin1[2]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011111111101110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntin1[3]~input_o\,
	datab => \cntin1[1]~input_o\,
	datac => \cntin1[0]~input_o\,
	datad => \cntin1[2]~input_o\,
	combout => \Mux6~0_combout\);

-- Location: LCCOMB_X3_Y1_N10
\Mux5~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \Mux5~0_combout\ = (!\cntin1[3]~input_o\ & ((\cntin1[1]~input_o\ & ((\cntin1[0]~input_o\) # (!\cntin1[2]~input_o\))) # (!\cntin1[1]~input_o\ & (\cntin1[0]~input_o\ & !\cntin1[2]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100000001010100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntin1[3]~input_o\,
	datab => \cntin1[1]~input_o\,
	datac => \cntin1[0]~input_o\,
	datad => \cntin1[2]~input_o\,
	combout => \Mux5~0_combout\);

-- Location: LCCOMB_X3_Y1_N28
\Mux4~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \Mux4~0_combout\ = (\cntin1[1]~input_o\ & (!\cntin1[3]~input_o\ & (\cntin1[0]~input_o\))) # (!\cntin1[1]~input_o\ & ((\cntin1[2]~input_o\ & (!\cntin1[3]~input_o\)) # (!\cntin1[2]~input_o\ & ((\cntin1[0]~input_o\)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101000101110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntin1[3]~input_o\,
	datab => \cntin1[1]~input_o\,
	datac => \cntin1[0]~input_o\,
	datad => \cntin1[2]~input_o\,
	combout => \Mux4~0_combout\);

-- Location: LCCOMB_X3_Y1_N6
\Mux3~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \Mux3~0_combout\ = (!\cntin1[3]~input_o\ & ((\cntin1[1]~input_o\ & (\cntin1[0]~input_o\ & \cntin1[2]~input_o\)) # (!\cntin1[1]~input_o\ & (\cntin1[0]~input_o\ $ (\cntin1[2]~input_o\)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100000100010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntin1[3]~input_o\,
	datab => \cntin1[1]~input_o\,
	datac => \cntin1[0]~input_o\,
	datad => \cntin1[2]~input_o\,
	combout => \Mux3~0_combout\);

-- Location: LCCOMB_X3_Y1_N24
\Mux2~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \Mux2~0_combout\ = (\cntin1[2]~input_o\ & (\cntin1[3]~input_o\)) # (!\cntin1[2]~input_o\ & (\cntin1[1]~input_o\ & ((\cntin1[3]~input_o\) # (!\cntin1[0]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101010001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntin1[3]~input_o\,
	datab => \cntin1[1]~input_o\,
	datac => \cntin1[0]~input_o\,
	datad => \cntin1[2]~input_o\,
	combout => \Mux2~0_combout\);

-- Location: LCCOMB_X3_Y1_N26
\Mux1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \Mux1~0_combout\ = (\cntin1[3]~input_o\ & ((\cntin1[1]~input_o\) # ((\cntin1[2]~input_o\)))) # (!\cntin1[3]~input_o\ & (\cntin1[2]~input_o\ & (\cntin1[1]~input_o\ $ (\cntin1[0]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011111010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntin1[3]~input_o\,
	datab => \cntin1[1]~input_o\,
	datac => \cntin1[0]~input_o\,
	datad => \cntin1[2]~input_o\,
	combout => \Mux1~0_combout\);

-- Location: LCCOMB_X3_Y1_N4
\Mux0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \Mux0~0_combout\ = (!\cntin1[3]~input_o\ & (!\cntin1[1]~input_o\ & (\cntin1[0]~input_o\ $ (\cntin1[2]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000100010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntin1[3]~input_o\,
	datab => \cntin1[1]~input_o\,
	datac => \cntin1[0]~input_o\,
	datad => \cntin1[2]~input_o\,
	combout => \Mux0~0_combout\);

-- Location: IOIBUF_X34_Y18_N1
\cntin2[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_cntin2(0),
	o => \cntin2[0]~input_o\);

-- Location: IOIBUF_X34_Y17_N15
\cntin2[3]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_cntin2(3),
	o => \cntin2[3]~input_o\);

-- Location: IOIBUF_X34_Y20_N8
\cntin2[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_cntin2(1),
	o => \cntin2[1]~input_o\);

-- Location: IOIBUF_X34_Y18_N15
\cntin2[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_cntin2(2),
	o => \cntin2[2]~input_o\);

-- Location: LCCOMB_X18_Y16_N0
\Mux13~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \Mux13~0_combout\ = (\cntin2[3]~input_o\) # ((\cntin2[1]~input_o\ & ((!\cntin2[2]~input_o\) # (!\cntin2[0]~input_o\))) # (!\cntin2[1]~input_o\ & ((\cntin2[2]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101111111111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntin2[0]~input_o\,
	datab => \cntin2[3]~input_o\,
	datac => \cntin2[1]~input_o\,
	datad => \cntin2[2]~input_o\,
	combout => \Mux13~0_combout\);

-- Location: LCCOMB_X18_Y16_N26
\Mux12~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \Mux12~0_combout\ = (!\cntin2[3]~input_o\ & ((\cntin2[0]~input_o\ & ((\cntin2[1]~input_o\) # (!\cntin2[2]~input_o\))) # (!\cntin2[0]~input_o\ & (\cntin2[1]~input_o\ & !\cntin2[2]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000000110010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntin2[0]~input_o\,
	datab => \cntin2[3]~input_o\,
	datac => \cntin2[1]~input_o\,
	datad => \cntin2[2]~input_o\,
	combout => \Mux12~0_combout\);

-- Location: LCCOMB_X18_Y16_N20
\Mux11~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \Mux11~0_combout\ = (\cntin2[1]~input_o\ & (\cntin2[0]~input_o\ & (!\cntin2[3]~input_o\))) # (!\cntin2[1]~input_o\ & ((\cntin2[2]~input_o\ & ((!\cntin2[3]~input_o\))) # (!\cntin2[2]~input_o\ & (\cntin2[0]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010001100101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntin2[0]~input_o\,
	datab => \cntin2[3]~input_o\,
	datac => \cntin2[1]~input_o\,
	datad => \cntin2[2]~input_o\,
	combout => \Mux11~0_combout\);

-- Location: LCCOMB_X18_Y16_N22
\Mux10~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \Mux10~0_combout\ = (!\cntin2[3]~input_o\ & ((\cntin2[0]~input_o\ & (\cntin2[1]~input_o\ $ (!\cntin2[2]~input_o\))) # (!\cntin2[0]~input_o\ & (!\cntin2[1]~input_o\ & \cntin2[2]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000100000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntin2[0]~input_o\,
	datab => \cntin2[3]~input_o\,
	datac => \cntin2[1]~input_o\,
	datad => \cntin2[2]~input_o\,
	combout => \Mux10~0_combout\);

-- Location: LCCOMB_X18_Y16_N8
\Mux9~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \Mux9~0_combout\ = (\cntin2[2]~input_o\ & (((\cntin2[3]~input_o\)))) # (!\cntin2[2]~input_o\ & (\cntin2[1]~input_o\ & ((\cntin2[3]~input_o\) # (!\cntin2[0]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntin2[0]~input_o\,
	datab => \cntin2[3]~input_o\,
	datac => \cntin2[1]~input_o\,
	datad => \cntin2[2]~input_o\,
	combout => \Mux9~0_combout\);

-- Location: LCCOMB_X18_Y16_N10
\Mux8~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \Mux8~0_combout\ = (\cntin2[3]~input_o\ & (((\cntin2[1]~input_o\) # (\cntin2[2]~input_o\)))) # (!\cntin2[3]~input_o\ & (\cntin2[2]~input_o\ & (\cntin2[0]~input_o\ $ (\cntin2[1]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101111011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntin2[0]~input_o\,
	datab => \cntin2[3]~input_o\,
	datac => \cntin2[1]~input_o\,
	datad => \cntin2[2]~input_o\,
	combout => \Mux8~0_combout\);

-- Location: LCCOMB_X18_Y16_N28
\Mux7~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \Mux7~0_combout\ = (!\cntin2[3]~input_o\ & (!\cntin2[1]~input_o\ & (\cntin2[0]~input_o\ $ (\cntin2[2]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000100000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cntin2[0]~input_o\,
	datab => \cntin2[3]~input_o\,
	datac => \cntin2[1]~input_o\,
	datad => \cntin2[2]~input_o\,
	combout => \Mux7~0_combout\);

ww_ledout1(0) <= \ledout1[0]~output_o\;

ww_ledout1(1) <= \ledout1[1]~output_o\;

ww_ledout1(2) <= \ledout1[2]~output_o\;

ww_ledout1(3) <= \ledout1[3]~output_o\;

ww_ledout1(4) <= \ledout1[4]~output_o\;

ww_ledout1(5) <= \ledout1[5]~output_o\;

ww_ledout1(6) <= \ledout1[6]~output_o\;

ww_ledout2(0) <= \ledout2[0]~output_o\;

ww_ledout2(1) <= \ledout2[1]~output_o\;

ww_ledout2(2) <= \ledout2[2]~output_o\;

ww_ledout2(3) <= \ledout2[3]~output_o\;

ww_ledout2(4) <= \ledout2[4]~output_o\;

ww_ledout2(5) <= \ledout2[5]~output_o\;

ww_ledout2(6) <= \ledout2[6]~output_o\;
END structure;


